The present invention relates to a technique for reducing power consumption of a processor system including a plurality of processors such as processing units called a central processing unit (CPU), a hardware engine (HWE) or a coprocessor, for example.
There has been a known technique for reducing power consumption of a CPU by lowering the frequency of a clock signal when the load in processing of the CPU is light (e.g., Japanese Unexamined Patent Publication No. 9-34599.) Also known is a technique for reducing power consumption and heat release of/from an entire system by turning off a power source of an associated unit when a decoded instruction is “no-operation” in a processor system including a plurality of units such as a CPU and a coprocessor (e.g., Japanese Unexamined Patent Publication No. 2000-112756.)
The above-mentioned technique of merely reducing the frequency of a clock signal is applicable when the processing load is light, but is not applicable when a high processing ability is required. Therefore, large reduction of power consumption of an entire system is not always achieved.
In addition, with the technique of turning off a power source for a unit which does not perform processing, power consumption in processing itself is not reduced, and thus great reduction of power consumption is not achieved as well.